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[cvs-checkins] pci/ tl/verilog/pci_tpram.v tl/verilog/wb_tpra ...

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] pci/ tl/verilog/pci_tpram.v tl/verilog/wb_tpra ...
From: OpenCores CVS Agent <cvs@www.lampret.com>
Date: Mon, 30 Sep 2002 16:22:30 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/09/30 16:22:30

Modified files:
	rtl/verilog    : pci_tpram.v wb_tpram.v 
	sim/rtl_sim/run: run_pci_sim_regr.scr 
Added files:
	sim/rtl_sim/bin: vs_file_list.lst 

Log message:
	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!

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