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[cvs-checkins] minirisc/ /README.txt erilog/core/alu.v erilog ...
CVSROOT: /home/oc/cvs
Module name: minirisc
Changes by: rudi 02/09/27 14:35:42
Modified files:
. : README.txt
verilog/core : alu.v presclr_wdt.v primitives.v
primitives_xilinx.v register_file.v risc_core.v
risc_core_top.v
verilog/testbench: prog_mem.v
Added files:
sim : run
verilog/testbench: test.v
Removed files:
verilog/core : test.v
Log message:
Minor update to newer devices ...
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