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[cvs-checkins] oc8051/sim/rtl_sim/src/verilog oc8051_uart_tes ...

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] oc8051/sim/rtl_sim/src/verilog oc8051_uart_tes ...
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Tue, 3 Sep 2002 14:06:22 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	oc8051
Changes by:	simont	02/09/03 14:06:22

Modified files:
	sim/rtl_sim/src/verilog: oc8051_uart_test.v oc8051_xram.v 

Log message:
	added signals ack, stb and cyc
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