CVSROOT: /home/oc/cvs Module name: oc8051 Changes by: markom 02/08/23 08:08:57 Modified files: rtl/verilog : oc8051_divide.v oc8051_top.v Log message: main divider logic was optimized not optimized by compiler, so I did it by hand -- To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml