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[cvs-checkins] ethernet/rtl/verilog eth_defines.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_defines.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Fri, 16 Aug 2002 21:09:49 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/08/16 21:09:49

Modified files:
	rtl/verilog    : eth_defines.v 

Log message:
	Defines for register width added. mii_rst signal in MIIMODER register
	changed.
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