CVSROOT: /home/oc/cvs Module name: mlite Changes by: rhoads 02/06/17 00:28:25 Modified files: vhdl : mem_ctrl.vhd Log message: Altera, added byte_sel_reg for tigher timing and avoid possible glitches -- To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml