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[cvs-checkins] i2c/ tl/verilog/i2c_master_bit_ctrl.v tl/vhdl/ ...

CVSROOT:	/home/oc/cvs
Module name:	i2c
Changes by:	rherveille	02/06/15 09:37:12

Modified files:
	rtl/verilog    : i2c_master_bit_ctrl.v 
	rtl/vhdl       : i2c_master_bit_ctrl.vhd 
Added files:
	sim/i2c_verilog/run: bench.vcd ncverilog.key ncverilog.log run 

Log message:
	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.

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