[cvs-checkins] ethernet/rtl/verilog eth_fifo.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	oc	02/04/22 15:46:14

Modified files:
	rtl/verilog    : eth_fifo.v 

Log message:
	Generic ram or Xilinx ram can be used in fifo (selectable by setting
	ETH_FIFO_XILINX in eth_defines.v).

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml