[cvs-checkins] vga_lcd/bench/verilog tests.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	vga_lcd
Changes by:	oc	02/04/20 11:58:16

Modified files:
	bench/verilog  : tests.v 

Log message:
	Changed testbench to reflect modified VGA timing generator.

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