[cvs-checkins] dbg_interface/rtl/verilog dbg_top.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	dbg_interface
Changes by:	mohor	02/04/17 13:16:45

Modified files:
	rtl/verilog    : dbg_top.v 

Log message:
	A block for checking possible simulation/synthesis missmatch added.

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