[cvs-checkins] ethernet/rtl/verilog eth_wishbone.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/03/02 20:12:48

Modified files:
	rtl/verilog    : eth_wishbone.v 

Log message:
	Byte ordering changed (Big Endian used). casex changed with case because
	Xilinx Foundation had problems. Tested in HW. It WORKS.

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