[cvs-checkins] ethernet/rtl/verilog eth_rxethmac.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	oc	02/02/15 14:44:34

Modified files:
	rtl/verilog    : eth_rxethmac.v 

Log message:
	RxAbort is an output. No need to have is declared as wire.

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