[cvs-checkins] ethernet/rtl/verilog eth_top.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/02/12 18:03:03

Modified files:
	rtl/verilog    : eth_top.v 

Log message:
	HASH0 and HASH1 registers added. Registers address width was
	changed to 8 bits.

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