[cvs-checkins] vga_lcd/rtl/verilog vga_wb_slave.v vga_wb_mast ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	vga_lcd
Changes by:	rherveille	02/02/07 06:42:11

Modified files:
	rtl/verilog    : vga_wb_slave.v vga_wb_master.v vga_fifo.v 
	                 vga_defines.v vga_csm_pb.v vga_colproc.v 
Added files:
	rtl/verilog    : vga_ssel.v vga_enh_top.v 
Removed files:
	rtl/verilog    : vga_top.v 

Log message:
	Fixed some bugs discovered by modified testbench
	Removed / Changed some strange logic constructions
	Started work on hardware cursor support (not finished yet)
	Changed top-level name to vga_enh_top.v

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