[cvs-checkins] or1k/mp3/rtl/verilog/or1200 or1200_alu.v or120 ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	02/01/28 02:16:10

Modified files:
	mp3/rtl/verilog/or1200: or1200_alu.v or1200_cpu.v or1200_ctrl.v 
	                        or1200_dc_fsm.v or1200_dc_top.v 
	                        or1200_dmmu_tlb.v or1200_dmmu_top.v 
	                        or1200_du.v or1200_except.v 
	                        or1200_freeze.v or1200_genpc.v 
	                        or1200_ic_fsm.v or1200_ic_top.v 
	                        or1200_if.v or1200_immu_tlb.v 
	                        or1200_immu_top.v or1200_top.v 
	                        or1200_tt.v 

Log message:
	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.

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