[cvs-checkins] ethernet/rtl/verilog eth_clockgen.v eth_crc.v ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/01/23 11:28:21

Modified files:
	rtl/verilog    : eth_clockgen.v eth_crc.v eth_defines.v 
	                 eth_maccontrol.v eth_macstatus.v eth_miim.v 
	                 eth_outputcontrol.v eth_random.v 
	                 eth_receivecontrol.v eth_register.v 
	                 eth_registers.v eth_rxcounters.v eth_rxethmac.v 
	                 eth_rxstatem.v eth_shiftreg.v 
	                 eth_sync_clk1_clk2.v eth_top.v 
	                 eth_transmitcontrol.v eth_txcounters.v 
	                 eth_txethmac.v eth_txstatem.v eth_wishbonedma.v 
	                 timescale.v 

Log message:
	Link in the header changed.

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