[cvs-checkins] or1k/mp3/rtl/verilog/or1200 or1200_defines.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	02/01/14 10:44:15

Modified files:
	mp3/rtl/verilog/or1200: or1200_defines.v 

Log message:
	Default ASIC configuration does not sample WB inputs.

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