[cvs-checkins] wb_dma/rtl/verilog wb_dma_ch_rf.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	wb_dma
Changes by:	rudi	01/10/30 03:06:21

Modified files:
	rtl/verilog    : wb_dma_ch_rf.v 

Log message:
	- Fixed problem where synthesis tools would instantiate latches instead of flip-flops

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