[cvs-checkins] ethernet/rtl/verilog eth_wishbonedma.v eth_txs ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	01/10/19 10:43:56

Modified files:
	rtl/verilog    : eth_wishbonedma.v eth_txstatem.v eth_txethmac.v 
	                 eth_txcounters.v eth_transmitcontrol.v 
	                 eth_top.v eth_sync_clk1_clk2.v eth_shiftreg.v 
	                 eth_rxstatem.v eth_rxethmac.v eth_rxcounters.v 
	                 eth_registers.v eth_register.v 
	                 eth_receivecontrol.v eth_random.v 
	                 eth_outputcontrol.v eth_miim.v eth_macstatus.v 
	                 eth_maccontrol.v eth_crc.v eth_clockgen.v 
Added files:
	rtl/verilog    : timescale.v 
Removed files:
	rtl/verilog    : eth_timescale.v 

Log message:
	eth_timescale.v changed to timescale.v This is done because of the
	simulation of the few cores in a one joined project.

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