CVSROOT: /home/oc/cvs Module name: pci Changes by: mihad 01/10/05 10:11:25 Added files: rtl/verilog : timescale.v Log message: Updated all files with inclusion of timescale file for simulation purposes. -- To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml