[cvs-checkins] mem_ctrl/rtl/verilog mc_rf.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	mem_ctrl
Changes by:	rudi	01/10/04 05:19:40

Modified files:
	rtl/verilog    : mc_rf.v 

Log message:
	Fixed Register reads
	Tightened up timing for register rd/wr

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