[cvs-checkins] i2c/ ench/verilog/i2c_slave_model.v ench/veril ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	i2c
Changes by:	rherveille	01/09/24 14:21:51

Added files:
	bench/verilog  : i2c_slave_model.v tst_bench_top.v 
	                 wb_master_model.v 
	doc            : i2c_rev03.pdf 
	doc/src        : I2C_specs.doc 
	rtl/verilog    : i2c_master_bit_ctrl.v i2c_master_byte_ctrl.v 
	                 i2c_master_defines.v i2c_master_top.v 
	                 timescale.v 
	rtl/vhdl       : I2C.VHD tst_ds1621.vhd wishbone_i2c_master.vhd 
Removed files:
	documentation  : I2C_specs.doc i2c_rev03.pdf 
	vhdl           : I2C.VHD tst_ds1621.vhd wishbone_i2c_master.vhd 

Log message:
	Created new directory structure.
	Added Verilog version.

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