[cvs-checkins] wb_prefetch_spram/rtl/verilog generic_spram.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	wb_prefetch_spram
Changes by:	lampret	01/09/23 07:02:15

Modified files:
	rtl/verilog    : generic_spram.v 

Log message:
	Temporarily changed artisan memory cell name to art_hssp_8192x32

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