[cvs-checkins] vga_lcd/rtl/verilog vga_wb_slave.v vga_wb_mast ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	vga_lcd
Changes by:	rherveille	01/09/17 13:59:26

Modified files:
	rtl/verilog    : vga_wb_slave.v vga_wb_master.v vga_vtim.v 
	                 vga_top.v vga_tgen.v vga_pgen.v vga_fifo_dc.v 
	                 vga_fifo.v vga_csm_pb.v vga_colproc.v ud_cnt.v 
	                 ro_cnt.v 
Added files:
	rtl/verilog    : vga_vga_and_clut_top.v generic_spram.v 
	                 generic_dpram.v 

Log message:
	Major rework.
	Included generic memory models.
	Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml