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[cvs-checkins] Import

CVSROOT:	/home/oc/cvs
Module name:	generic_memories
Changes by:	oc	01/09/14 11:57:14

Log message:
    Major cleanup.
    Files are now compliant to Altera & Xilinx memories.
    Memories are now compatible, i.e. drop-in replacements.
    Added synthesizeable generic FPGA description.
    Created "generic_memories" cvs entry.
    
    Status:
    
    Vendor Tag:	rherveille
    Release Tags:	initial
    
    N generic_memories/rtl/verilog/generic_spram.v
    N generic_memories/rtl/verilog/generic_dpram.v
    
    No conflicts created by this import
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