[cvs-checkins] wb_dma/ ench/verilog/test_bench_top.v ench/ver ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	wb_dma
Changes by:	rudi	01/09/07 17:34:38

Modified files:
	bench/verilog  : test_bench_top.v tests.v wb_mast_model.v 
	rtl/verilog    : wb_dma_defines.v wb_dma_top.v 
	sim/rtl_sim/bin: Makefile 
	syn/bin        : comp.dc lib_spec.dc 

Log message:
	Changed reset to active high.

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