[cvs-checkins] ata/ tl/verilog/ocidec-1/atahost_top.v ench/ve ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ata
Changes by:	rudi	01/08/16 12:01:05

Modified files:
	rtl/verilog/ocidec-1: atahost_top.v 
Added files:
	bench/verilog  : ata_device.v test_bench_top.v tests.v 
	                 wb_mast_model.v wb_model_defines.v 
	                 wb_slv_model.v 
	sim/rtl_sim/bin: Makefile 
	syn/bin        : comp.dc design_spec.dc lib_spec.dc read.dc 

Log message:
	- Added Test Bench
	- Added Synthesis scripts for Design Compiler
	- Fixed minor bug in atahost_top

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