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[cvs-checkins] uart16550/rtl/verilog uart_receiver.v uart_reg ...



CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/08/15 22:14:06

Modified files:
	rtl/verilog    : uart_receiver.v uart_regs.v uart_top.v 
	                 uart_transmitter.v 

Log message:
	changed pad top level port names.

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