[cvs-checkins] wb_dma/ oc/README.txt oc/STATUS.txt ench/veril ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	wb_dma
Changes by:	rudi	01/07/29 10:57:03

Modified files:
	doc            : README.txt STATUS.txt 
Added files:
	bench/verilog  : test_bench_top.v tests.v wb_mast_model.v 
	                 wb_model_defines.v wb_slv_model.v 
	doc            : dma_doc.pdf 
	rtl/verilog    : wb_dma_ch_arb.v wb_dma_ch_pri_enc.v 
	                 wb_dma_ch_rf.v wb_dma_ch_sel.v wb_dma_de.v 
	                 wb_dma_defines.v wb_dma_inc30r.v wb_dma_rf.v 
	                 wb_dma_top.v wb_dma_wb_if.v wb_dma_wb_mast.v 
	                 wb_dma_wb_slv.v 
	sim/rtl_sim/bin: Makefile 
	syn/bin        : comp.dc design_spec.dc lib_spec.dc read.dc 
Removed files:
	test_bench     : test_bench_top.v tests.v wb_mast_model.v 
	                 wb_model_defines.v wb_slv_model.v 
	verilog        : wb_dma_ch_arb.v wb_dma_ch_pri_enc.v 
	                 wb_dma_ch_rf.v wb_dma_ch_sel.v wb_dma_de.v 
	                 wb_dma_defines.v wb_dma_primitives.v 
	                 wb_dma_rf.v wb_dma_top.v wb_dma_wb_if.v 
	                 wb_dma_wb_mast.v wb_dma_wb_slv.v 

Log message:
	1) Changed Directory Structure
	2) Added restart signal (REST)

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