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[cvs-checkins] ata/verilog/ocidec-1 controller.v counter.v pi ...

CVSROOT:	/home/oc/cvs
Module name:	ata
Changes by:	rherveille	01/07/02 10:57:26

Modified files:
	verilog/ocidec-1: controller.v counter.v pio_tctrl.v 

Log message:
	Fixed some incomplete port lists. Fixed some Verilog related issues.
	Design now compiles completely.

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