[cvs-checkins] uart16550/verilog UART_wb.v UART_TX_FIFO.v UAR ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/05/17 20:34:19

Modified files:
	verilog        : UART_wb.v UART_TX_FIFO.v UART_top.v UART_test.v 
	                 UART_RX_FIFO.v UART_regs.v UART_defines.v 
	                 FIFO_inc.v 
Added files:
	verilog        : UART_transmitter.v UART_receiver.v 
Removed files:
	verilog        : UART_FIFO_t.v UART_FIFO.v ToDo.txt 

Log message:
	First 'stable' release. Should be sythesizable now. Also added new header.