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[cvs-checkins] uart16550/verilog UART_regs.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] uart16550/verilog UART_regs.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Sat, 12 May 2001 20:00:57 +0200
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/05/12 20:00:56

Modified files:
	verilog        : UART_regs.v 

Log message:
	Fixed minor bugs and finished interrupt logic. Now compiles.

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