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[cvs-checkins] hdlc/DOCS hdlc_project.tex
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[cvs-checkins] hdlc/CODE/TOP/core hdlc.vhd RxBuff.vhd RxFCS.v ...
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[cvs-checkins] hdlc/CODE/TOP/scripts/nc-sim build_hdlc_top.cs ...
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[cvs-checkins] hdlc/CODE/TOP/scripts/model build_hdlc_top.do ...
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[cvs-checkins] hdlc/CODE/TOP/tb hdlc_tb.vhd RxTop_tb.vhd TxTo ...
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[cvs-checkins] hdlc/CODE LIBS/hdlc_components_pkg.vhd RX/CORE ...
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[cvs-checkins] hdlc/CODE/TOP/tb
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[cvs-checkins] hdlc/CODE/TOP/stim
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[cvs-checkins] hdlc/CODE/TOP/scripts/nc-sim
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[cvs-checkins] hdlc/CODE/TOP/scripts/model
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[cvs-checkins] hdlc/CODE/TOP/scripts
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[cvs-checkins] hdlc/CODE/TOP/core
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[cvs-checkins] hdlc/CODE/TOP
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[cvs-checkins] wb_vga/TestBench vga_core_v2_TB.vhd
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[cvs-checkins] wb_vga/ /accel.vhd /compile.sh /mem_reader.vhd ...
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[cvs-checkins] wb_vga/. vga_core_v2.vhd
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[cvs-checkins] wb_tk/. technology.vhd wb_test.vhd
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[cvs-checkins] i2c/. wishbone_i2c_master.vhd
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[cvs-checkins] ata/ cidec1/counter.vhd cidec1/revision_histor ...
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[cvs-checkins] wb_vga/ /hv_sync.vhd estBench/vga_chip_TB.vhd
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[cvs-checkins] wb_vga/ /mem_reader.vhd /sync_gen.vhd /vga_chi ...
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[cvs-checkins] or1k/gen_or1k_isa Makefile gen_or1k_isa result ...
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[cvs-checkins] or1k/docs openrisc_arch3.doc openrisc_arch3.pdf
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[cvs-checkins] Import
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[cvs-checkins] or1k/docs openrisc_arch3.doc openrisc_arch3.pdf
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[cvs-checkins] ata/ocidec2 revision_history.txt
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[cvs-checkins] ata/ocidec1 revision_history.txt
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[cvs-checkins] ata/ocidec1 records.vhd
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[cvs-checkins] ata/ocidec2 records.vhd
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[cvs-checkins] ata/ocidec3 records.vhd
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[cvs-checkins] ata/ocidec3 revision_history.txt
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[cvs-checkins] ata/ cidec1/ata.vhd cidec1/controller.vhd cide ...
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[cvs-checkins] gpio/docs gpio_spec.pdf
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[cvs-checkins] Import
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[cvs-checkins] Import
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[cvs-checkins] or1k/or1ksim/testbench dhrystone/dhry.c test1/ ...
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[cvs-checkins] or1k/or1ksim/testbench/uos/user3
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[cvs-checkins] or1k/or1ksim/testbench/uos/user1
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[cvs-checkins] or1k/or1ksim/testbench/uos/libc
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[cvs-checkins] or1k/or1ksim/testbench/uos/kernel
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[cvs-checkins] or1k/or1ksim/testbench/uos README
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[cvs-checkins] or1k/or1ksim/testbench/uos
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[cvs-checkins] or1k/or1ksim Makefile.am Makefile.in configure ...
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[cvs-checkins] or1k/or1ksim/tick Makefile Makefile.am Makefil ...
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[cvs-checkins] or1k/or1ksim/tick
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[cvs-checkins] or1k/binutils/include/opcode or32.h
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] or1k/or1ksim/cpu/or1k or32.h
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] or1k/or1ksim/cpu/or1k spr_defs.h
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] or1k/docs openrisc_arch3.pdf
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] or1k/docs openrisc_arch3.doc openrisc_old.pdf
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] or1k/docs
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] or1k/gen_or1k_isa/sources chop_html.c gen_or1k ...
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] or1k/or1ksim testbench/test1/test1.c cpu/or1k/ ...
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] or1k/gen_or1k_isa Makefile README gen_or1k_isa ...
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[cvs-checkins] or1k/gen_or1k_isa/sources gen_or1k_isa.c or1k_ ...
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] or1k/or1ksim toplevel.c
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[cvs-checkins] or1k/or1ksim/support dumpverilog.c
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[cvs-checkins] or1k/or1ksim/cache Makefile.in
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[cvs-checkins] or1k/or1ksim/cpu common/execute.h or1k/or32.h ...
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[cvs-checkins] or1k/or1ksim/cpu/or1k except.c
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[cvs-checkins] or1k/binutils/include/opcode or32.h
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[cvs-checkins] or1k/or1ksim/testbench dhrystone/Makefile dhry ...
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[cvs-checkins] or1k/or1ksim/testbench/dhrystone
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[cvs-checkins] or1k/or1ksim/testbench/test1
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[cvs-checkins] or1k/or1ksim/testbench
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[cvs-checkins] or1k/or1ksim/testbench dhry.or32
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