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Re: [oc] VHDL Problem

To: Matija Habek <cores@opencores.org>
Subject: Re: [oc] VHDL Problem
From: Héctor Orón Martínez <hecormar@teleco.upv.es>
Date: Fri, 11 Jul 2003 20:16:57 +0200
In-Reply-To: <3f0c8f34.43f4.0@net.hr>
Organization: ETSIT-UPV
References: <3f0c8f34.43f4.0@net.hr>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

Estimado Matija,

Con fecha miércoles, 09 de julio de 2003, 23:55:00, escribió:

MH> Can I simulate a pull-up resistor in VHDL using Graphic Editor and how?

MH> --
MH> Besplatni e-mail - http://webmail.iskon.hr/
MH> --
MH> To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml

I think what you are looking for is a buffer tri-state, it is possible
to write it on VHDL, but i have never used a graphic VHDL.
:-D

-- 
Saludos,
 Héctor                            mailto:hecormar@teleco.upv.es

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References:
- [oc] VHDL Problem
  - From: "Matija Habek" <mhabek@net.hr>

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