Re: [oc] constraints while programming in VHDL

[John Sheahan <jrsheahan@optushome.com.au>]

On Mon, 2003-06-16 at 22:11, ritika_dua@yahoo.com wrote:
> 
> 
> sir, i want to know how we can use delays in the vhdl code, as the 
> delays can't be synthesized .
> --

they are useful in testbenches and models. Simulation in general.
But not in code to be synthesized.

Do I misunderstand the question?
john
. 

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