[oc] The use of both edge of the clock.

[<nico@seul.org>]

At school, we learn that design must be full synchronous on one edge of
the clock to avoid any timing hasard.

But, i see very often some chip interface that sample or deliver the data
at the folling edge of the clock. Does this trick very usefull ? Does it
generate dozen of "false path" for synthetiser ?

What is the common rules and pitfall about using this ?

nicO


--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml