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Re: [oc] Verilog
On Tuesday 11 February 2003 01:21, Ho, Wen Jei x4297 wrote:
> Somebody in OpenCore wrote something like:
>
> A <= B & C | D & E & (~F | F & G) & ~H;
>
> Could Verilog guru put in "(" and ")" for me?
Don't think you need to be guru. The standard boolean precedence would apply;
A <= (B & C) | (D & E & (~F | F & G) & ~H);
Niclas
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- References:
- [oc] Verilog
- From: "Ho, Wen Jei x4297" <who1@rockwellcollins.com>