[oc] Re: Questions in DMA IP Core ?

[Rudolf Usselmann <rudi@asics.ws>]

On Fri, 2003-02-07 at 09:48, NansonHuang@ITRI.ORG.TW wrote:
> 
> 
>  Hi, dear electronics elites,
> 
>  I have studied the DMA IP core spec. and organized some questions to
> discuss with you used to use. In Fig. 2, there is a link between
> Prioritizing Arbiter and DMA engine. What kind of information does it

Highest Priority Level

> convey ? Is it necessary ?

Yes

> In Fig. 10, it illustrates the so called " back
> to back transfer ", how to explain it ?

DMA keeps the bus between transfers -> back-to-back

> In table 3 CSR register, it defines the PAUSE bit to pause DMA engine. If
> once it paused, all channels are realted to and if the DMA relinquish the
> bus. If it resume after that, how does DMA act ? DMA will continue the
> un-completed transfer or re-start it. I am confused to the operation

It works just like the "Pause" button on your VCR.

> situation. In table 6 Channel CSR Register,
> there are 3 INT source Channel transferred CHK_SZ, Done and Error. Besides,
> there are ERR and DONE bit as well. Could we combine them into one copy ?

No, you can not combine them - both provide totally
different information.

> They both indicate the status of DMA. At last, it defines the Channel
> Address Mask Registers. I dont understand according to the explanation
> listed in spec. Could you give me more information on it ?

Try running some of the included test.

>  Thanks in advances and your time,
> 
>  Nanson



rudi
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