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[oc] About module path delay

hi:
  What's difference between positive polarity and negative 
polarity on defining module path delay? After simulation 
with two description, i can't find the difference.

  The code as below:
    
    ...
    assign o = i; 
   //if using verilog-XL,must be "buf (o, i)". but i don't why

    specify 
      (i +=> o) = (40, 20);
      (i -=> o) = (40, 20);
    endspecify
    ...



Regars
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