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RE: [oc] New! FFT core, transform gain issue
I made a mistake, I will correct it soon.
For the limitation, the following is my consideration,
1.
For the 1024 point fft, the input is a Gauss process,
which variance is sigma,
after FFT, which variance change to sigma*29.4/32.
2.
because the ram is 12 bit width, so after every butterfly,
I scale the cordic out to 12 bit. The cordic gain is 1.65,
I div the cordic out 4, and limit it to 12 bit.
So after every butterfly, signal decrease 1.65/4. At the
last butterfly, the signal does not div 4, so the output is 14 bit.
3.
If the input is single frequence, should reserve 3 bit.
If the input is Gauss signal, may reserve 1 or 2 bit depends on
the demand.
regards,
zhaom
----- Original Message -----
From: h.larsen@r...
To: cores@o...
Date: Wed, 20 Nov 2002 11:25:45 +0100
Subject: RE: [oc] New! FFT core, transform gain issue
>
>
> Hi,
> Thanks for your answers concerning the FFT gain.
> I still think the documentation has an error in the table
> concerning the
> gain:
> The IFFT "this one" collumn should read 0.0287 and the FFT "this
> one" should
> read 29.4
> for the 1024 point. Its the revers in the version ive got. Or have
> I still
> not understood it?
>
> regards
> henning
>
> As requested by Saumil Merchant: below is the testbench I have
used
> in my
> evaluation
> -- START VHDL
> -- Simple "testbench" for cfft1024x12. It is realy just an
> excitation of
> inputs
> -- The output has to be evaluated manually. run for 125 us with
> current
> settings.
> -- Input is a dual sinsoid with constant amplitudes, and a DC
> value.
> -- Input is real valued only. A calculation of the power spectrum,
> and a
> frequency bin
> -- counter is included, but no reordering of output sequence is
> performed.
> -- Frequencies are easy to select such that a minimum of spill into
> side
> bins is obtained.
> -- Beware of the posibilty of saturation in the output. For single
> sinsoide,
> the saturation limit
> -- is 2^14/29.4=557 units of input amplitude. Is it lower if more
> frequencies plus DC are involved?
> -- Not clear excactly how to determine what the limit will be in
> this case,
> but in order to
> -- efficiently use the core this issue has to be clarified. Using
> an ADC of
> 12 bit with
> -- full scale input would therefore not be appropriate!
> -- For 12 bit ADC, and guarantee agains saturation the output
> should be able
> to hold
> -- the input multiplied by the gain of 29.4. Therefore the input
> width is
> -- Wfft_in= ceiling(log2(29.4*2^Wadc))-2 =
> ceiling(log2(29.4*4096))-2=15 or
> -- in general 3 bits more than the ADC bit width. Wrong or right?
> -- henning larsen
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> USE ieee.std_logic_arith.all;
> USE ieee.math_real.all;
> USE ieee.std_logic_signed.all;
>
> ENTITY cfft1024x12_tester1 IS
> END cfft1024x12_tester1 ;
> ARCHITECTURE tester OF cfft1024x12_tester1 IS
> -- Component Declarations
> COMPONENT cfft1024X12
> PORT (
> clk : IN STD_LOGIC ;
> rst : IN STD_LOGIC ;
> start : IN STD_LOGIC ;
> inv : IN std_logic ;
> Iin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
> Qin : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
> inputbusy : OUT STD_LOGIC ;
> outdataen : OUT STD_LOGIC ;
> Iout : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
> Qout : OUT STD_LOGIC_VECTOR (13 DOWNTO 0)
> );
> END COMPONENT;
>
> constant Tck_half : time:=10 ns;
> constant Tckhalf : real:=10.0e-9;-- real value eqv of time,
there
> is
> some conversion function
> -- for this but could not
> find/remember.
> constant ampl1 : real:=100.0;-- max amplitude is roughly
> 550=2^14/29.4 to avoid sturation in output
> constant ampl2 : real:=200.0; -- .. but see intro comments
> constant f1 : real := 100.0/TckHalf/2.0/1024.0;-- bin number
=100
> constant f2 : real := 33.0/TckHalf/2.0/1024.0;-- bin number
=33
> constant dc : real:=100.0;--bin number=0
>
> signal c1,c2,cout: real;
> signal clock : std_logic:='0';
> signal reset : std_logic:='0';
> signal start : std_logic:='0';
> signal inv : std_logic ;
> signal Iin : STD_LOGIC_VECTOR (11 DOWNTO 0);
> signal Qin : STD_LOGIC_VECTOR (11 DOWNTO 0);
> signal inputbusy : STD_LOGIC:='0' ;
> signal outdataen : STD_LOGIC:='0' ;
> signal Iout : STD_LOGIC_VECTOR (13 DOWNTO 0);
> signal Qout : STD_LOGIC_VECTOR (13 DOWNTO 0);
> signal amp : real; -- power spectrum
> signal bitRev : STD_LOGIC_VECTOR (9 DOWNTO 0);--
bin
> counter
>
> BEGIN
> -- Instance port mappings.
> I0 : cfft1024X12
> PORT MAP (
> clk => clock,
> rst => reset,
> start => start,
> inv => inv,
> Iin => Iin,
> Qin => Qin,
> inputbusy => inputbusy,
> outdataen => outdataen,
> Iout => Iout,
> Qout => Qout
> );
>
>
> ----------------------------------------------------------------------------
> --
> -- control signals ,setup
> clock <= not clock after Tck_half;
> reset <= '1', '0' after 2*Tck_half;
> start <= '0', '1' after 3*Tck_half, '0' after 5*Tck_half;-- only
> one FFT is
> done
> inv <= '0';-- FFT
>
>
> ----------------------------------------------------------------------------
> --
> sin_gen: process(clock, reset)
> variable tid : real;
> variable TM : real :=0.0 ;
> begin
> if Reset = '1' then
> c1 <= 0.0;
> c2 <= 0.0;
> Iin<="000000000000" ;
> Qin<="000000000000" ;
> TM := 0.0;
> tid := TM;
> else
> if clock'event and clock = '1' then
> TM := TM + Tckhalf*2.0;
> tid := TM;
> c1 <= (ampl1 * sin
(2.0*math_pi*f1*tid));
> c2 <= (ampl2 * sin
(2.0*math_pi*f2*tid));
> cout <= c1+c2+dc;
> Iin <=
> conv_std_logic_vector(integer(cout),Iin'length);
> Qin <="000000000000" ;
> end if;
> end if;
> end process sin_gen;
>
> ----------------------------------------------------------------------------
> --
> --Output power spectrum, normalized with the gain of 29.4
> amp <= sqrt(real(CONV_integer(Iout)) * real(CONV_integer(Iout))
> + real(CONV_integer(Qout)) * real(CONV_integer
(Qout)))/29.4;
>
> ----------------------------------------------------------------------------
> --
> -- radix 4 bit reversed counter
> radix4cnt: process (clock)
> variable cntr: std_logic_vector ( 9 downto 0);
> begin
> if rising_edge(clock) then
> if outdataen='1' then
> cntr:=unsigned(cntr)+1;
> else
> cntr:=(others => '0');
> end if;
> for k in 1 to ((10) / 2) loop
> bitRev(2*k-2)<= cntr(10-2*k);
> bitRev(2*k-1)<= cntr(10-(-1+2*k));
> end loop;
> end if;
> end process radix4cnt;
>
> END tester;
> -- END VHDL
>
> > -----Original Message-----
> > From: sradio@o... [mailto:sradio@o... ]
> > Sent: 20. november 2002 09:02
> > To: cores@o...
> > Subject: Re: [oc] New! FFT core, transform gain issue
> >
> >
> >
> >
> > ----- Original Message -----
> > From: h.larsen@r...
> > To: cores@o...
> > Date: Tue, 19 Nov 2002 16:56:37 +0100
> > Subject: [oc] New! FFT core, transform gain issue
> >
> > >
> > >
> > > Hi,
> > >
> > > I have tested the cfft core, but found that the gain is
> 29.4 both
> > > in N=1024
> > > FFT and IFFT, whereas the documentation says it should be
> 0.0287
> > in
> > > FFT
> > > mode, and 29.4 in IFFT mode.
> >
> > 0.0287=29.4/1024,
> >
> > In Matlab, the ifft pocess divide N. (:
> >
> > >
> > > I simply supply a real ampliude of a sine wave to the
> input of the
> > > cfft1024X12: Something like->
> > > Iin=A*sin(2pi*F*t) + DC;
> > > Qin=0;
> > >
> > > and measure the output amplitude (FFT or IFFT, no
> difference,
> > > except to
> > > phase of output). It gives a peak at bin 0 of DC*29.4 and
> two peaks
> > > at the
> > > proper bins with an amplitude of 14.7*A each, which makes
> sense
> > > only if the
> > > gain is 29.4=14.7*2 (two bins).
> > >
> > > Anybody who have tried similar things?
> > >
> > > In particular a comment from the briliant designer ZHAO
> Ming would
> > > be very
> > > welcome.
> > >
> > > regards
> > > henning larsen
> > > Electronics des. engineer
> > > Risoe national laboratory
> > > Denmark
> > >
> >
>
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