[oc] sram vhdl help

[edwinstuff@yahoo.com]

I tried to implement a 35 X 120 SRAM in the xilinx Spartan chip, but
it was too big. Could anybody give me suggestion to minimize the
number of slices of the xilinx chip in vhdl?  the max slices is 1200.
 The map is 
    <-- 24 X 5 = 120 -->
  A ***** ***** ..  *****
  | ***** ***** ..  *****
 35   :     :
  |
  V ***** ***** ..  *****

my vhdl code...........
--///////////////////////////////////////////////////////////////////
if Cs_b = '1' then IO <= "11111111";
			else
				if We_b'event and We_b = '1' then
			   		    tempInt := vec2int(Address);
						RAM1(tempInt) <= IO;
					wait for 2 ns;		
				end if;

				if We_b = '1' then
				        tempInt := vec2int(Address);
						IO <= RAM1(tempInt);
				else IO <= "11111111";
				end if;
			end if;
			wait on We_b, Cs_b, Address;
--
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