RE: [oc] Vera Query

[vlsi_champ@indiatimes.com]

then can u think of VEra?????????



----- Original Message ----- 
From: sphuynh <sphuynh@m... > 
To: "'cores@o... '" <cores@o... > 
Date: Wed, 13 Nov 2002 09:59:46 -0700 
Subject: RE: [oc] Vera Query 

> 
> 
> Oops, sorry, I was thinking of Verilog :) 
> 
> -----Original Message----- 
> From: sphuynh 
> Sent: Wednesday, November 13, 2002 9:53 AM 
> To: 'cores@o... ' 
> Subject: RE: [oc] Vera Query 
> 
> 
> Humm... 
> 
> always @ (posedge int_in) begin 
> 	int_cnt = int_cnt + 1; 
> 	n_inta; 
> end 
> 
> 
> 
> -----Original Message----- 
> From: vlsi_champ@i...  [mailto:vlsi_champ@i... ] 
> Sent: Wednesday, November 13, 2002 2:49 AM 
> To: cores@o...  
> Subject: [oc] Vera Query 
> 
> 
> Hello Friends, 
> 
> I have a query in Vera. I am hanged up at a point in my project. It 
> wud 
> be nice of u if u can help me out ASAP. 
> 
> The query is as follow: 
> 
> How to do some operation/s on the positive edge of an input?? For 
> instance, on every positive edge of an input signal int_in, the 2 
> operations are to be performed; 
> 1) increment counter int_cnt, and 
> 2) call a task named n_inta ( ). How to do this? 
> 
> 
> 
> Thanks in advance, 
> 
> Regards, 
> 
> VLSI CHAMP 
> 
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