RE: [oc] FPGA- Constrains

I'm Curius , why did you cancle synplicity ?

As for constrain I assume you already tried the speed and balanced (sometime better than speed) as well as different effort (sometime 2 or 3 give better result than 5 or extra 1/2) and using input/output IO FF etc etc (also if you are using slow device you might wnat to try to see what faster device give tho' I would think the usualy 30M you should be able to use also the slwoest device)

if so why not do quick sanity check and check that each module meet the frequnacy you want with margin on the IO for either FF or logic depend how the code go from one module to the other.

if all pass than you might only need to do some floorplaning but if you already get violation than you can see it more clearly and it should be easier to fix. (as it might be something like only sample the output from memorey block or something simple like this)

how big is the design and to which device do you target it ?

have a nice day

Illan

-----Original Message-----
From: R. Ramakrishna [mailto:rayaprolu_rk@yahoo.com]
Sent: Tuesday, October 29, 2002 8:48 PM
To: cores@opencores.org
Subject: Re: [oc] FPGA- Constrains

Hi All,

This is regarding the help I wanted to have on Constraining a design on FPGA::

Thank you very much for your suggestions. I was not well and so could not continue my work on the matter for 1 week.

Thank you John in particular for your suggestions.

>>>FPGA express is not really designed for this. Its pretty knobless

Yes, I agree that FPGA Express is pretty knobless in these issues and so, we are looking for a new synth tool-- FPGA compiler II is the one I'd wish to have. Leonardo's are Synplicity's tools optimise too much and that does'nt suit my design. We have evaluated them separately. So we were forced to use FPGA express that comes with Xilinx's ISE4.1i.

>>>Is the 14MHz (or whatever you achieved) taking into account the false paths? if it is, then ignoring the false paths won't gain you much - if anything. If it is not - then STA better.

Yes, the frequency of 14MHz was achieved with false paths taken into consideration by applying TIG ( Timing Ignore ) on those paths using the Constraints Editor of Xilinx's ISE.

>>>14MHz (??) is probably a whole lot faster than the simulator anyway - running lots of vectors at that speed would seem more useful than putting lots of effort into tweaking fpga synthersis - perhaps?

BUT my requirement is that I need to work at atleast 30MHz!!

Now comming to what we could achieve:: We made the tool recognise every clock net in our design by instantiating BUFGDLL for the clock input and then instantiating a BUFG or a CLKDLL wherever the clock needed to have a larger fanout or needed to be doubled or phase needed to be shifted. This was done throughout the design. Then in the UCF, we just applied PERIOD constraint on the input and the output of the BUFGDLL or CLKDLL and the TIG was applied on the false paths. This improved the frequency to nearly 20MHz from 10-14MHz.

I would be very happy if any one can suggest me some thing to extend my work so as to get a final 30MHz on FPGA.

Thank you All again and hope to get some more info on the matter.

Rayaprolu RK

Associate Engineer.

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