RE: [oc] VHDL uart(9600,8,N,1) help. urgent

["Igor Mohor" <igorm@opencores.org>]

You should divide your clock to 11.05MHz/(16 * 9600) = 72

You forgot to divide by 16.

Regards,
	Igor

> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of ckh827@hotmail.com
> Sent: 2. oktober 2002 11:01
> To: cores@opencores.org
> Subject: [oc] VHDL uart(9600,8,N,1) help. urgent
> 
> 
> I'm currently working on the Vhdl for Xilinx's FPGA.  The output is 
> characters which will be sent to RS232 port.  The chip's frequency is
> 11.05 Mhz. Since it's (9600,8,N,1),  I tried to use a counter that
> count to 1151(11.05MHz/9600 = 1151) and then output a 'high' in order
> to generate 9600 baud rate.  However, what I got is always junks.
> In vhdl, I use Wait on clk9600 = '1' to send one bit at a time and I
> used for ten times because its total is ten bits(start +data+ stop
> bit). Is this the correct way to do this? And also, there are only
> (transmit,receive and ground pins going through rs232 com1 port)
> 
> I need some help as soon as possible.  Any help is appreciated.
> 
> Could anybody give me some suggestions to code this program.
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