Re: [oc] Synchron Moore State Machine

[Torsten Weber <t.weber@hhi.de>]

magnus.pihl@lightmarelaser.com wrote:

> >>"How do you know  you use one-hot encoding ?? "
> I use the free program Quartus 2.0. I can simply set it to run in One-Hot
> mode. The "message" after synthesis informs that it has used one-hot
> encoding.
>
> >> Simulate your design.
> I have. It looks good. That is the problem.

Did you try to simulate on gate level after P&R?
I've got 2 more questions/aspects regarding your design: Did you use synchronous or asynchronous
reset? If it is asynchronous, does your state machine a state switch without any condition after
the reset (e.g. while reset your state machine goes to "init", and if reset is inactive your state
machine switches unconditioned to "start")? In this case it can happen that the asynchronous reset
hits one register of your state machine short time after clock edge and other before (you have
different clock and reset delays on the connections). This can result in a wrong state transition
vector reaching a state which isn't defined (e.g. more than one '1' in a one-hot state machine ->
"when others" clause can help).
So it is better to have a (synchronous) generated signal to generate a switch condition for your
state machine, the easiest solution is to define a single signal with reset value '0' and first
clock transition to '1'.

>
> Best regards,
> Magnus

Best regards
  Torsten

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml