Re: [oc] Synchron Moore State Machine

[Richard Herveille <richard@asics.ws>]

> Dear VHDL folks,
>
> Using a CPLD, I have made a FIFO buffert control for an external 512kB
> SRAM.  The CPLD controls the read/write cycles. The cycles are
> controlled by a Synchron Moore State Machine.
>
> The State Machine uses One-Hot encoding.

For a CPLD one-hot encoding isn't usually the best solution.
If you use a FPGA, then choose on-hot.
If you use VHDL to create a statemachine, you usually use enumerated types. 
How do you know  you use one-hot encoding ??

> "When others", is therefore not used.

This is a nice trap. Not necessarily for synthesis, but it is for simulation.
Each signal can have multiple states (e.g. '0', '1', 'L', 'H', 'Z', 'X', 'U' 
etc). The simulator compares these, and usually complains when you don't 
define the "when others =>" state. Anyway I think it is a good thing to 
always add it. Most synthesizers give you a note or a waring that the 
"others" state is never reached. In that case you know you designed your 
statemachine just like you want it. If it doesn't you probably mist a state 
somewhere (or your synthesizer is so dumb it doesn't issue a note/warning).

>
> Problem: The system locks with both read and write active, which is a
> state that I have not defined.
>
> Question: How do I solve this problem, and why do this problem occur?

Simulate your design.

>
> Best regards,
> Magnus

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