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Re: [oc] type error in expression

one other observation...  the assign statement after the ELSE does not need to be there and may not even be legal syntax.  Here's how I would have written this:

ss_0 <= '0' WHEN ss_2_a  = '0' and ss_2_b = '0' and ss_2_c = '0'
and  ss_2 = '0' ELSE '1';
      
ss_4 <= '0' WHEN ss_2_a = '0' and ss_2_b = '0' and  ss_2_c = '1' and
ss_2 = '0' ELSE '1';
      
ss_7 <= '0' WHEN ss_2_a = '1' and ss_2_b = '1' and ss_2_c = '1' and
ss_2 = '0' ELSE '1';


On Fri, 2002-06-14 at 21:38, Nanda wrote: 
what is the signal ss_0 type ?
is it integer or std_logic ?

after the ELSE u have assigned a integer , '1' is a bit and 1 is a
integer.
-- cheers

On Fri, 14 Jun 2002 shumad@celiant.com wrote:

> I'm just beginning with VHDL and was writing code for a
> 3 to 8 demux. I keep getting the following error:
> 
> "type error in expression" for these lines of my code:
> 
> ss_0 <= '0' WHEN ss_2_a  = '0' and ss_2_b = '0' and ss_2_c = '0' 
> and  ss_2 = '0' ELSE ss_0 <= 1;
> 	
> ss_4 <= '0' WHEN ss_2_a = '0' and ss_2_b = '0' and  ss_2_c = '1' and 
> ss_2 = '0' ELSE ss_4 <= 1;
> 	
> ss_7 <= '0' WHEN ss_2_a = '1' and ss_2_b = '1' and ss_2_c = '1' and 
> ss_2 = '0' ELSE ss_7 <= 1;
>  
> 
> ss_2_a, ss_2_b, ss_2_c and ss_2 are all declared as in bits;
> ss_0, ss_4, ss_7 are declared as inout bits;
> 
> Can someone pls help me.
> Thanks
> --
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~~~~
K.G.Nanda Kumar
Senior Research Engineer
Satellite Communication
Centre for Development Of Telematics
71/1,millers road
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ph:2263399 Extn 324

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