[oc] type error in expression

[shumad@celiant.com]

I'm just beginning with VHDL and was writing code for a
3 to 8 demux. I keep getting the following error:

"type error in expression" for these lines of my code:

ss_0 <= '0' WHEN ss_2_a  = '0' and ss_2_b = '0' and ss_2_c = '0' 
and  ss_2 = '0' ELSE ss_0 <= 1;
	
ss_4 <= '0' WHEN ss_2_a = '0' and ss_2_b = '0' and  ss_2_c = '1' and 
ss_2 = '0' ELSE ss_4 <= 1;
	
ss_7 <= '0' WHEN ss_2_a = '1' and ss_2_b = '1' and ss_2_c = '1' and 
ss_2 = '0' ELSE ss_7 <= 1;
 

ss_2_a, ss_2_b, ss_2_c and ss_2 are all declared as in bits;
ss_0, ss_4, ss_7 are declared as inout bits;

Can someone pls help me.
Thanks
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