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Re: [oc] Wishbone Bus

To: cores@opencores.org
Subject: Re: [oc] Wishbone Bus
From: Shawn Tan <shawn.tan@aeste.net>
Date: Thu, 13 Jun 2002 10:47:01 +0800
References: <200206122107.XAA25554@iza.mr2.si>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org
User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:0.9.9) Gecko/20020313

klm681@mail.usask.ca wrote:
> How do you connect the Wishbone Bus when you only have 1 IP core?  
> In PCI-bus core, it includes WB, but what if there are no other cores 
> which need interfacing?

Why do you need the WB bus if you've got no other cores to connect to??
The WB is an SOC bus..

with metta,
Shawn Tan.


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References:
- [oc] Wishbone Bus
  - From: klm681@mail.usask.ca

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