Re: [oc] PUSH/POP Instructions on RISC?

["Andras Tantos" <andras_tantos@yahoo.com>]

> Why are the push/pop instructions never found on risc processors? If a
> processor has two write backs to the register file it doesn't need that
> much more hardware to do post/pre-increment/decrement memory reference
> instructions. Is there a special reason for not having these
> instructions? It's simpler than a scaled memory reference reg+c*reg.

Hi!

I'm not a RISC processor expert, but at least in the ARM instruction set
there is some support for stacks. For example the instruction

stmfd sp!, {fp, ip, lr, pc}

will store fp, ip, lr, pc on the stack (pointed by sp), using pre-decrement
indexing. The counterpart for example would look like this:

ldmea fp, {fp, sp, pc}

fp, sp, etc. are general registers, but gcc has aliases for their common
uses.

Regards,
Andras Tantos

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